P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface)

Table 26.  Avalon-MM Interface Summary
Avalon-MM Type Data Bus Width Max Burst Size Byte Enable Granularity Max Outstanding Read Request
Bursting Slave 512 bits 8 cycles byte 64
Bursting Master 512 bits 8 cycles byte 32
Read Data Mover Write Master 512 bits 8 cycles dword N/A
Write Data Mover Read Master 512 bits 8 cycles dword 128
Control Register Access 32 bits 1 cycle byte 1

These interfaces are standard Avalon® interfaces. For timing diagrams, refer to the Avalon Interface Specifications.

Note: The number of read requests issued by the Write Data Mover's Avalon-MM Read Master is controlled by the assertion of waitrequest by the connected slave(s). The Read Master can handle 128 outstanding cycles of data. You cannot set this parameter in Platform Designer. The slave needs to correctly back-pressure the master once it cannot handle the incoming requests.
Note: The 512-bit Bursting Slave interface does not support transactions where byte enables are set to 0.

Did you find the information on this page useful?

Characters remaining:

Feedback Message