P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38)

This register controls which errors are forwarded as internal uncorrectable errors.

Table 84.  Uncorrectable Internal Error Mask Register
Bits Register Description Default Value Access
[31:13] Reserved 0x0 RO
[12] Mask for Debug Bus Interface (DBI) access error. 0x1 RWS
[11] Mask for Uncorrectable ECC error from Config RAM block. 0x1 RWS
[10:9] Reserved 0x0 RO
[8] Mask for RX Transaction Layer parity error reported by the IP core. 0x1 RWS
[7] Mask for TX Transaction Layer parity error reported by the IP core. 0x1 RWS
[6] Mask for Uncorrectable Internal error reported by the FPGA. 0x1 RWS
[5] Mask for Configuration Error detected in CvP mode. This bit is only available for Port 0 ( PCIe* Gen4 x16), but not for the other Ports. 0x0 RWS
[4:0] Reserved 0x0 RO
Note: The access code RWS stands for Read Write Sticky, meaning that the value is retained after a soft reset of the IP core.

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