P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)

The CRA interface provides access to the control and status registers of the Avalon-MM bridge. This interface has the following properties:
  • 32-bit data bus
  • Supports a single transaction at a time
  • Supports single-cycle transactions (no bursting)
Note: When the Avalon-MM Hard IP for PCIe IP Core is in Root Port mode, and the application logic issues a CfgWr or CfgRd via the CRA interface, it needs to fill the Tag field in the TLP Header with the value 0x10 to ensure that the corresponding Completion gets routed to the CRA interface correctly. If the application logic sets the Tag field to some other value, the Avalon-MM Hard IP for PCIe IP Core does not overwrite that value with the correct value.
Table 42.  Avalon-MM CRA Slave Interface
Signal Name Direction Description Platform Designer Interface Name
cra_read_i I Read enable. cra
cra_write_i I

Write request.

cra_address_i[14:0] I  
cra_writedata_i[31:0] I Write data. The current version of the CRA slave interface is read-only. Including this signal as a part of the Avalon-MM interface makes future enhancements possible.
cra_readdata_o[31:0] O Read data.
cra_byteenable_i[3:0] I Byte enable.
cra_waitrequest_o O Wait request to hold off additional requests.
cra_chipselect_i I Chip select signal to this slave.
cra_irq_o O Interrupt request. A port request for an Avalon-MM interrupt.

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