P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

1.2. Features

The P-Tile Avalon® memory mapped IP for PCI Express supports the following features:
  • Configurations supported:
    Table 1.  Configurations Supported by the P-Tile Avalon® memory mapped IP for PCI Express
      Gen3/Gen4 x16 Gen3/Gen4 x8 Gen3/Gen4 x4
    Endpoint (EP) Yes Yes N/A
    Root Port (RP) 1 N/A Yes
    Note: Gen1/Gen2 configurations are supported via link down-training.
  • Support for 256-bit and 512-bit data paths.
  • 512-bit data path with 250 MHz interfaces to user logic to ease timing closure for Gen3 x16.
  • Support for a single function (PF0).
  • High-throughput Bursting Avalon® memory mapped Slave (BAS).
    • Byte enables with byte granularity.
  • High-throughput Bursting Avalon® memory mapped Master (BAM).
  • Support for up to 7 BARs, including expansion ROM BAR.
  • Support for byte enables with byte granularity.
  • Support for up to 64 outstanding Non-Posted requests.
  • Summary of outstanding Non-Posted requests supported:
    Table 2.  Outstanding Non-Posted Requests Supported
    Ports Active Cores Outstanding Non-Posted Requests
    0 x16 64, 512 (*)
    1 x8 64
    2 and 3 x4 64
    Note: (*) : 512 outstanding Non-Posted requests support may be available in a future Intel® Quartus® Prime release.
  • Data movers with high throughput for DMA support
    • Move data using PCIe Memory Read and Memory Write packets.
    • Bursting Avalon® memory mapped Master interfaces for data path.
    • Byte enables with dword granularity.
    • Avalon® streaming interfaces for control and status.
    • DMA transfers of 1 dword to (1 MB - 1 dword) in 1 dword increments.
    • All addresses are dword-aligned.
  • Bursts of up to 8 cycles (512 bytes) for the Bursting Avalon® memory mapped Master, Bursting Avalon® memory mapped Slave and the data movers.
  • Support for Max Payload Size values of 128, 256 and 512 bytes.
  • Support for Max Read Request Size values of 128, 256 and 512 bytes.
  • Available as a Platform Designer component with standard Avalon® interfaces.
  • MSI and MSI-X.
  • Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
  • You cannot change the pin allocations for the P-Tile Avalon® memory mapped IP for PCI Express* in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB.
  • Supports Autonomous Hard IP mode.
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
      Note: Unless Readiness Notifications mechanisms are used, the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Modular implementation allowing users to enable the required features for a specific application. For example:
    • Simultaneous support for DMA modules and high-throughput Avalon® memory mapped Slaves and Masters.
    • Avalon® memory mapped Slave for easy access to the whole PCIe address space.
  • VCS is the only simulator supported in the 20.2 release of Intel® Quartus® Prime. Other simulators may be supported in a future release.
Note: Throughout this User Guide, the term Avalon® -MM may be used as an abbreviation for the Avalon® memory mapped interface or IP.
1 These configurations may be available in a future release of Intel® Quartus® Prime.

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