P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.6.3.1. Implementing MSI-X Interrupts

Section 6.8.2 of the PCI Local Bus Specification describes the MSI-X capability and table structures. The MSI-X capability structure points to the MSI-X Table structure and MSI-X Pending Bit Array (PBA) registers. The BIOS sets up the starting address offsets and BAR associated with the pointer to the starting address of the MSI-X Table and PBA registers.
  1. Host software sets up the MSI-X interrupts in the Application Layer by completing the following steps:
    1. Host software reads the Message Control register at 0x050 register to determine the MSI-X Table size. The number of table entries is the <value read> + 1.
      The maximum table size is 2048 entries. Each 16-byte entry is divided in 4 fields as shown in the figure below. For multi-function variants, BAR4 accesses the MSI-X table. For all other variants, any BAR can access the MSI-X table. The base address of the MSI-X table must be aligned to a 4 KB boundary.
      Note that multi-function support is not available in the current release of Intel® Quartus® Prime.
    2. The host sets up the MSI-X table. It programs MSI-X address, data, and masks bits for each entry as shown in the figure below.
      Figure 25. Format of MSI-X Table
    3. The host calculates the address of the <n th > entry using the following formula:
       
      				  nth_address = base address[BAR] + 16<n>
  2. When Application Layer has an interrupt, it drives an interrupt request to the IRQ Source module.
  3. The IRQ Processor reads the entry in the MSI-X table.
    1. If the interrupt is masked by the Vector_Control field of the MSI-X table, the interrupt remains in the pending state.
    2. If the interrupt is not masked, IRQ Processor sends Memory Write Request to the TX slave interface. It uses the address and data from the MSI-X table. If Message Upper Address = 0, the IRQ Processor creates a three-dword header. If the Message Upper Address > 0, it creates a 4-dword header.
  4. The host interrupt service routine detects the TLP as an interrupt and services it.

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