P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.7. Hot Plug Interface (RP Only)

Note: The Hot Plug interface is not supported in the 20.2 release of Intel® Quartus® Prime. It may be supported in a future release.

Hot Plug support means that the device can be added to or removed from a system during runtime. The Hot Plug Interface in the P-Tile Avalon® -MM IP for PCIe allows an Intel FPGA with this IP to safely provide this capability.

This section describes the signals reported by the on-board hot plug components in the Downstream Port. This interface is available only if the Slot Status Register of the PCI Express Capability Structure is enabled.

Refer to the Slot Status Register of the PCI Express Capability Structure for additional information.
Table 49.  Hot Plug Interface
Signal Name Direction Description Clock Domain EP/RP
sys_atten_button_pressed_i I Attention Button Pressed. Indicates that the system attention button was pressed, and sets the Attention Button Pressed bit in the Slot Status Register. p<n>_app_clk RP
sys_pwr_fault_det_i I Power Fault Detected. Indicates the power controller detected a power fault at this slot. p<n>_app_clk RP
sys_mrl_sensor_chged_i I MRL Sensor Changed. Indicates that the state of the MRL sensor has changed. p<n>_app_clk RP
sys_pre_det_chged_i I Presence Detect Changed. Indicates that the state of the card presence detector has changed. p<n>_app_clk RP
sys_cmd_cpled_int_i I Command Completed Interrupt. Indicates that the Hot Plug controller completed a command. p<n>_app_clk RP
sys_pre_det_state_i I

Indicates whether or not a card is present in the slot.

0 : slot is empty.

1 : card is present in the slot.

p<n>_app_clk RP
sys_mrl_sensor_state_i I

MRL Sensor State. Indicates the state of the manually operated retention latch (MRL) sensor.

0 : MRL is closed.

1 : MRL is open.

p<n>_app_clk RP
sys_eml_interlock_engaged_i I Indicates whether the system electromechanical interlock is engaged, and controls the state of the electromechanical interlock status bit in the Slot Status Register. p<n>_app_clk RP
sys_aux_pwr_det_i I

Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present.

Refer to the Device Status Register in the PCI Express Capability Structure.

p<n>_app_clk RP

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