P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.6. Interrupt Interface

The P-Tile Avalon® -MM IP for PCI Express* supports Message Signaled Interrupts (MSI), MSI-X interrupts, and legacy interrupts. MSI and legacy interrupts are mutually exclusive.

Legacy interrupts, MSI, and MSI-X interrupts are all controlled and generated externally to the Avalon® -MM IP to ensure total flexibility of allocating interrupt resources based on the user’s application needs.

To support domain-isolation, legacy interrupt messages, MSI, and MSI-X TLPs need to be sent with the appropriate source IDs.

The following figure shows an example integrating an external interrupt controller with the P-Tile Avalon® -MM IP. The interrupt controller takes interrupt requests from the external DMA controller as well as those from the user application.

Figure 20. Example of an Interrupt Controller Integrated with an Endpoint P-Tile Avalon® -MM IP for PCI Express* IP Core

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