P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

3.3. Avalon-MM Settings

Table 22.   Avalon® -MM Parameters
Parameter Value Default Value Description
Endpoint Settings
Enable Bursting Slave Mode True/False False Enable bursting Avalon® -MM Slave Interface. This will enable the Endpoint mode (where the IP's BAS and BAM modules are enabled, but its Data Movers are not enabled).
Address width of Read Data Mover {10:64} 64

Address width of Read Data Mover.

Address width of Write Data Mover {10:64} 64

Address width of Write Data Mover.

Export interrupt conduit interfaces True/False False Export internal signals to support generation of Legacy Interrupts/multiple MSI/MSI-X.
Address width of Bursting Master {10:64} 64

Only present in Root Port mode.

In Endpoint modes, this parameter is set by the largest BAR address width.

Root Port Settings
Avalon® -MM address width

32-bit

64-bit

64-bit Selects the Avalon® -MM address width.
Address width of accessible PCIe memory space (TXS) 1 - 64 32 Selects the address width of accessible memory space.
Enable burst capability for Avalon® -MM Master Port True/False False Enable burst capabilities for the BAR0 RXM. If this option is set to True, the RXM port will be a bursting master. Otherwise, this RXM will be a single Dword master.

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