P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.2.1. Interface Clock Signals

Table 24.  Interface Clock Signals
Name I/O Description EP/RP Clock Frequency
p<n>_app_clk (where n = 0, 1, 2, 3) O This is the application clock generated from coreclkout_hip or from the same source as refclk. This is a per-port signal. EP/RP

Native Gen3: 250 MHz

Native Gen4: 350 MHz ( Intel® Stratix® 10 DX) / 400 MHz ( Intel® Agilex™ )

The frequencies given above are the maximum frequencies. The frequencies available vary depending on the configurations that the IP is in. For more details, refer to .

coreclkout_hip O

This is an internal clock only that is planned to be removed in a future release of the Intel FPGA P-tile Avalon® Memory-mapped IP for PCI Express. The Application Layer must use the p<n>_app_clk instead.

The frequency depends on the data rate and the number of lanes being used.

EP/RP

Native Gen3: 250 MHz

Native Gen4: 350 MHz ( Intel® Stratix® 10 DX) / 400 MHz ( Intel® Agilex™ )

refclk[1:0] I

These are the input reference clocks for the IP core. These clocks must be free-running.

For more details on how to connect these clocks, refer to the section Clock Sharing in Bifurcation Modes.

EP/RP

100 MHz ± 300 ppm

When the Enable SRIS Mode parameter is enabled in the IP Parameter Editor, the P-Tile Avalon® -MM IP can communicate with a link partner whose clock domain is not synchronized to the refclk domain of the P-Tile. In this mode of operation, P-Tile and its link partner can both have their own spread spectrum clocks.

p<n>_hip_reconfig_clk (where n = 0, 1, 2, 3) I Clock for the hip_reconfig interface. This is an Avalon® -MM interface. It is an optional interface that is enabled when the Enable HIP dynamic reconfiguration of PCIe registers option in the PCIe Configuration, Debug and Extension Options tab is enabled. EP/RP

50 MHz - 125 MHz (range)

100 MHz (recommended)

xcvr_reconfig_clk I Clock for the PHY reconfiguration interface. This is an Avalon® -MM interface. This optional interface is enabled when you turn on the Enable PHY reconfiguration option in the Top-Level Settings tab. This interface is shared among all the cores. EP/RP

50 MHz - 125 MHz (range)

100 MHz (recommended)

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