P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)

Table 77.  Intel-Defined VSEC Capability Header
Bits Register Description Default Value Access
[31:20]

Next Capability Pointer. Value is the starting address of the next Capability Structure implemented, if any. Otherwise, NULL. Refer to the Configuration Address Map.

Variable RO
[19:16]

Capability Version. PCIe specification-defined value for VSEC Capability Version.

0x1 RO
[15:0]

Extended Capability ID. PCIe specification-defined value for VSEC Extended Capability ID.

0x000B RO

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