P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents
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A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)

Table 78.  Intel-Defined VSEC Capability Header
Bits Register Description Default Value Access

Next Capability Pointer. Value is the starting address of the next Capability Structure implemented, if any. Otherwise, NULL. Refer to the Configuration Address Map.

Variable RO

Capability Version. PCIe specification-defined value for VSEC Capability Version.

0x1 RO

Extended Capability ID. PCIe specification-defined value for VSEC Extended Capability ID.

0x000B RO