P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

6.1. Hardware

Typically, PCI Express link-up involves the following steps:
  1. Link training
  2. BIOS enumeration and data transfer

The following sections describe the flow to debug link issues during the hardware bring-up. Intel recommends a systematic approach to diagnosing issues as illustrated in the following figure.

Additionally, you can use the P-Tile Debug Toolkit for debugging the PCIe links when using the P-Tile Avalon® -MM IP for PCI Express. The P-Tile Debug Toolkit includes the following features:
  • Protocol and link status information.
  • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.
Figure 34. PCI Express Debug Flow Chart

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