P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

3.2.2.4. MSI Capabilities

Table 17.  MSI Capabilities
Parameter Value Default Value Description
PF0 Enable MSI True/False False

Enables MSI functionality for PF0.

If this parameter is True, the Number of MSI messages requested parameter will appear allowing you to set the number of MSI messages.

PF0 MSI Extended Data Capable True/False False Enables or disables MSI extended data capability for PF0.
PF0 Number of MSI messages requested

1

2

4

8

16

32

1 Sets the number of messages that the application can request in the multiple message capable field of the Message Control register.

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