P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

1.6. IP Core and Design Example Support Levels

The following table shows the support levels of the Avalon-MM IP core and design example in Intel® Stratix® 10 DX devices.

Table 7.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Intel® Stratix® 10 DX DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support
EP RP EP RP
Gen4 x16 512-bit S C T H (††) S C T H (†) (††)
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††)
Gen3 x16 512-bit S C T H (††) S C T H (†) (††)
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††)
Note: (†) The design example available in the 20.4 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Intel® Quartus® Prime.

The following table shows the support levels of the Avalon-MM IP core and design example in Intel® Agilex™ devices.

Table 8.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Intel® Agilex™ DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support
EP RP EP RP
Gen4 x16 512-bit S C T H (††) S C T H (†) (††)
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††)
Gen3 x16 512-bit S C T H (††) S C T H (†) (††)
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††)
Note: (†) The design example available in the 20.4 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Intel® Quartus® Prime.

Did you find the information on this page useful?

Characters remaining:

Feedback Message