P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.1.3. PCI Express Capability Structures

The layouts of the most basic Capability Structures are provided below. Refer to the PCI Express Base Specification for more information about these registers.
Figure 54. Power Management Capability Structure - Byte Address Offsets and Layout
Figure 55. MSI Capability Structure
Figure 56. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Figure 57. MSI-X Capability Structure
Figure 58. PCI Express AER Extended Capability Structure

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