P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface

The High Performance Avalon® -MM Slave has a 256-bit-wide data bus. It supports up to 16-cycle bursts with dword granularity byte enable on the first and last cycles of a write burst and for single-cycle read bursts. It also supports optional address mapping when the address bus is less than 64-bit wide.

This interface is optional. You enable it by turning On the Enable Bursting Slave option in the GUI.

Table 40.  High Performance Avalon® -MM Slave (HPTXS) Interface
Signal Name Direction Description Platform Designer Interface Name
hptxs_address_i [hptxs_address_width_hwtcl-1:0] I Byte address. Bits [4:0] are assumed to be zeros. hptxs_slave
hptxs_byteenable_i [31:0] I Specifies the valid bytes for a write command.
hptxs_read_i I When asserted, specifies a TX Avalon® -MM slave read request.
hptxs_readdata_o[255:0] O This bus contains the read completion data.
hptxs_write_i I When asserted, specifies a TX Avalon® -MM slave write request.
hptxs_writedata_i[255:0] I This bus contains the Avalon® -MM data for a write command.
hptxs_waitrequest_o O When asserted, indicates that the Avalon® -MM slave port is not ready to respond to a read or write request.
hptxs_readdatavalid_o O When asserted, indicates that the read data is valid.
hptxs_burstcount_i[4:0] I

When asserted, the value on the response signal is a valid write response.

Writeresponsevalid is only asserted one clock cycle or more after the write command is accepted.

There is at least a one clock cycle latency from command acceptance to the assertion of writeresponsevalid.

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