Visible to Intel only — GUID: fui1546645473355
Ixiasoft
Visible to Intel only — GUID: fui1546645473355
Ixiasoft
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit
This interface reads data from the Avalon-MM Read Master interface and writes it to the Host memory.
The wrdm_address_o value is set within the descriptor source address.
Signal Name | Direction | Description | Platform Designer Interface Name |
---|---|---|---|
wrdm_pfnum_o[1:0] | O |
Physical function number.
|
|
wrdm_waitrequest_i | I | When asserted, indicates that the Avalon® -MM slave is not ready to respond to a request. waitrequestAllowance = 4 The master can still issue 4 transfers after wrdm_waitrequest_i is asserted. |
wrdm_master |
wrdm_read_o | O | When asserted, indicates the master is requesting a read transaction. | |
wrdm_address_o[63:0] | O | Specify the byte address regardless of the data width of the master. | |
wrdm_burstcount_o[3:0] | O | The master uses these signals to indicate the number of transfers in each burst. | |
wrdm_byteenable_o[63:0] | O | Specify the valid bytes of wrdm_writedata_o[511:0]. Each bit corresponds to a byte in wrdm_writedata_o[511:0]. | |
wrdm_readdatavalid_i | I | Asserted by the slave to indicate that the wrdm_readdata_i[511:0] signals contain valid data in response to a previous read request. | |
wrdm_readdata_i[511:0] | I | Data signals for read transfers. | |
wrdm_response_i[1:0] | I | The response signals are optional signals that carry the response status.
Note: Because the signals are shared, an interface cannot issue or accept a write response and a read response in the same clock cycle.
The following encodings are available:
For read responses:
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