P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3. Avalon® -MM Interface

The figures below provide the top-level block diagrams of the P-Tile Avalon® -MM IP with all interfaces while operating in Endpoint mode with Data Movers or in Endpoint mode. These interfaces are described in more details in following sections.

Figure 17. P-Tile Avalon® -MM IP for PCIe in Endpoint Mode with Data Movers Top-Level Block Diagram
Figure 18. P-Tile Avalon® -MM IP for PCIe in Endpoint Mode Top-Level Block Diagram

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