P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
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4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)

In Gen3 x4 and Gen4 x4 Root Port modes, the IP core uses the 256-bit Avalon® -MM bridge instead of the 512-bit Avalon® -MM bridge for the performance purpose. In Root Port mode, DMA functionalities are not available. The table below shows the interfaces for the P-tile 256-bit Avalon® -MM bridge.

Table 39.  Summary of Interfaces for the 256-bit Avalon® -MM Bridge
Interface Name Data Width Burst Count Width Byte Enable Width Wait Request
Bursting Master 256 5 32 Yes

Non-Bursting Slave

(optional)

32 N/A 4 Yes

Bursting Slave

(optional)

256 5 32 Yes
Control Register Access (CRA) 32 N/A 4 Yes

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