P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents

4.10.1. Address Map for the User Avalon-MM Interface

The User Avalon® -MM interface provides access to the configuration registers and the IP core registers. This interface includes an 8-bit data bus and a 21-bit address bus (which contains the byte addresses).

There are two methods to access the configuration registers:
  • Using direct User Avalon® -MM interface (byte access)
  • Using the Debug (DBI) register access (dword access). This method is useful when you need to read/write the entire 32 bits at one time (Counter/ Lane Margining, etc.)

The following diagram and table show the address offsets for physical function 0 (PF0), User Avalon® -MM Port Configuration Register and Debug (DBI) Register.

Figure 28. Address Map for the User Avalon® -MM Interface
Table 55.  Configuration Space Offsets
Registers User Avalon® -MM Offsets Comments
Physical function 0 0x0000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16, x8 and x4 cores.
User Avalon-MM Port Configuration Register 0x104068 Refer to User Avalon-MM Port Configuration Register (Offset 0x104068) for more details.
Debug (DBI) Register 0x104200 to 0x104204 Refer to Using the Debug Register Interface Access for more details.

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