P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
ID
683268
Date
7/14/2021
Public
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
4.1. Overview
4.2. Clocks and Resets
4.3. Avalon® -MM Interface
4.4. Serial Data Interface
4.5. Hard IP Status Interface
4.6. Interrupt Interface
4.7. Hot Plug Interface (RP Only)
4.8. Power Management Interface
4.9. Configuration Output Interface
4.10. Hard IP Reconfiguration Interface
4.11. PHY Reconfiguration Interface
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.2.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.2.3. Intel Marker (Offset 08h)
A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.2.6. General Purpose Control and Status Register (Offset 0x30)
A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.2.9. Correctable Internal Error Status Register (Offset 0x3C)
A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access)
Targeting PF Configuration Space Registers
User application needs to specify the offsets of the targeted PF registers.
For example, if the application wants to read the MSI Capability Register of PF0, it will issue a Read with address 0x0050 to target the MSI Capability Structure of PF0.
Figure 29. PF Configuration Space Registers Access Timing Diagram
Targeting VSEC Registers
User application needs to program the VSEC field (0x104068 bit[0]) first. Then all accesses from the user Avalon® -MM interface starting at offset 0xD00 will be translated to VSEC configuration space registers.
Figure 30. VSEC Registers Access Timing Diagram