P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
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4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks

The Read Data Mover has two Avalon® -ST sink interfaces to receive the descriptors that define the data transfers to be executed. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.

The descriptor format for the Read Data Mover is described in the section Descriptor Format for Data Movers.

Note: The user application is responsible for performing the scheduling between priority and normal queues. No arbitration is performed inside the Read Data Mover.
Table 30.  Read Data Mover Avalon® -ST Normal Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
rddm_desc_ready_o O When asserted, this ready signal indicates the normal descriptor queue in the Read Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. rddm_desc
rddm_desc_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.
rddm_desc_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : single destination 3

[147] : reserved

[146] : reserved

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination Avalon® -MM address

[63:0]: source PCIe address

Table 31.  Read Data Mover Avalon® -ST Priority Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
rddm_prio_ready_o O When asserted, this ready signal indicates the priority descriptor queue in the Read Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. rddm_prio
rddm_prio_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the priority descriptor queue. On each cycle where this signal is active, the queue samples the data.
rddm_prio_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : single destination

[147] : reserved

[146] : reserved

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination Avalon® -MM address

[63:0]: source PCIe address

The Read Data Mover internally supports two queues of descriptors. The priority queue has absolute priority over the normal queue. Use it carefully to avoid starving the normal queue.

If the Read Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue as soon as it has completed the current descriptor. The Read Data Mover resumes processing the descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon® -ST source interface.

The Read Data Mover handles one descriptor at a time. When a descriptor has been processed (the memory command has been issued to the PCIe link), the Read Data Mover will read the next descriptor from the priority or normal descriptor interface.

Note: There is no buffer to store descriptors inside the Read Data Mover. In Intel's DMA design example, the buffer is located in the external DMA controller and supports up to 128 descriptors.

Software should only send new descriptors when the Read Data Mover has processed all previously sent descriptors. The P-Tile Avalon® -MM IP indicates the completion of the Read Data Mover's data processing by performing an immediate write to the system memory using its Write Data Mover. For more details, refer to the Read DMA Example section in the P-tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide (see the link in the Related Information below).

3 When the single destination bit is set, the same destination address is used for all the transfers. If the bit is not set, the address increments for each transfer.

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