P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.2.6. General Purpose Control and Status Register (Offset 0x30)

This register provides up to eight I/O pins each for Application Layer Control and Status requirements. This feature supports Partial Reconfiguration of the FPGA fabric. Partial Reconfiguration only requires one input pin and one output pin. The other seven I/Os make this interface extensible.

Table 82.  General Purpose Control and Status Register
Bits Register Description Default Value Access
[31:16] Reserved. N/A RO
[15:8] General Purpose Status. The Application Layer can read these status bits. These bits are only available for Port 0 ( PCIe* Gen4 x16). They are blocked for the other Ports. 0x00 RO
[7:0] General Purpose Control. The Application Layer can write these control bits. These bits are only available for Port 0 ( PCIe* Gen4 x16). They are blocked for the other Ports. 0x00 RW

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