Visible to Intel only — GUID: eyn1540248671330
Ixiasoft
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
4.1. Overview
4.2. Clocks and Resets
4.3. Avalon® -MM Interface
4.4. Serial Data Interface
4.5. Hard IP Status Interface
4.6. Interrupt Interface
4.7. Hot Plug Interface (RP Only)
4.8. Power Management Interface
4.9. Configuration Output Interface
4.10. Hard IP Reconfiguration Interface
4.11. PHY Reconfiguration Interface
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.2.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.2.3. Intel Marker (Offset 08h)
A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.2.6. General Purpose Control and Status Register (Offset 0x30)
A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.2.9. Correctable Internal Error Status Register (Offset 0x3C)
A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
Visible to Intel only — GUID: eyn1540248671330
Ixiasoft
A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)
This read-only register returns the JTAG Silicon ID. Intel programming software uses this JTAG ID to ensure that is is using the correct SRM Object File (*.sof).
These registers are only good for Port 0 ( PCIe* Gen4 x16). They are blocked for the other Ports.
Bits | Register Description | Default Value6 | Access |
---|---|---|---|
[127:96] | JTAG Silicon ID DW3 | Unique ID | RO |
[95:64] | JTAG Silicon ID DW2 | Unique ID | RO |
[63:32] | JTAG Silicon ID DW1 | Unique ID | RO |
[31:0] | JTAG Silicon ID DW0 | Unique ID | RO |
6 Because the Silicon ID is a unique value, it does not have a global default value.