P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)

This read-only register returns the JTAG Silicon ID. Intel programming software uses this JTAG ID to ensure that is is using the correct SRM Object File (*.sof).

These registers are only good for Port 0 ( PCIe* Gen4 x16). They are blocked for the other Ports.

Table 80.  JTAG Silicon ID Registers
Bits Register Description Default Value6 Access
[127:96] JTAG Silicon ID DW3 Unique ID RO
[95:64] JTAG Silicon ID DW2 Unique ID RO
[63:32] JTAG Silicon ID DW1 Unique ID RO
[31:0] JTAG Silicon ID DW0 Unique ID RO
6 Because the Silicon ID is a unique value, it does not have a global default value.

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