P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
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4.4. Serial Data Interface

The P-Tile Avalon® -MM IP for PCIe natively supports 4, 8, or 16 PCIe lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes.

Table 43.  Serial Data Interface
Signal Name Direction Description
tx_p_out[<b>-1:0], tx_n_out[<b>-1:0] O Transmit serial data outputs using the High Speed Differential I/O standard.
rx_p_in[<b>-1:0], rx_n_in[<b>-1:0] I Receive serial data inputs using the High Speed Differential I/O standard.
Note:

The value of the variable b depends on which configuration is active (1x16, 2x8 or 4x4).

  • For 1x16, b = 16.
  • For 2x8, b = 8.
  • For 4x4, b = 4.

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