P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

2.2.4.2. Endpoint Mode

In this mode, the external master (in user logic) sends memory reads and writes upstream via the Bursting Slave. The following modules are enabled:
  • Bursting Slave (in bursting mode)
  • Bursting Master (in non-bursting mode)
Figure 11. P-Tile Avalon® -MM IP in Endpoint Mode

The external Avalon® -MM master can be a custom DMA controller that uses the Bursting Slave in the IP core to send memory reads and writes upstream. These memory reads and writes can be up to 512-bytes long. The reordering buffer in the IP core reorders the Completion TLPs received over the PCIe link and sends them to the Bursting Slave.

The Bursting Master provides the host with access to the registers and memory in the Avalon® -MM address space of the FPGA. It converts PCIe memory reads and writes to Avalon® -MM reads and writes.

Registers in the custom DMA controller can be programmed by software via the Bursting Master port.

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