P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.6.1. Legacy Interrupts

If legacy interrupts are enabled at IP configuration time, the user’s interrupt controller generates legacy interrupts by asserting the intx_req_i input signal which causes the PCIe Hard IP to send the corresponding interrupt message. Use of legacy interrupts to signal the completion of DMA transfers is not recommended as their ordering with respect to the DMA traffic is not guaranteed.

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