P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.3.3. Read Data Mover Status Avalon® -ST Source

Table 32.  Read Data Mover Status -ST Source
Signal Name Direction Description Platform Designer Interface Name
rddm_tx_data_o[31:0] O

[31:16]: reserved

[15]: error

[14:12]: application specific

[11:9] : reserved

[8] : priority

[7:0]: descriptor ID

rddm_tx
rddm_tx_valid_o O Valid status signal

This interface does not have a ready input. The application logic must always be ready to receive status information for any descriptor that it has sent to the Read Data Mover.

The Read Data Mover copies over the application specific bits in the rddm_tx_data_o bus from the corresponding descriptor. A set priority bit indicates that the descriptor is from the priority descriptor sink.

A status word is output on this interface when the processing of a descriptor has completed, including the reception of all completions for all memory read requests.

Did you find the information on this page useful?

Characters remaining:

Feedback Message