P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

1.4. Device Family Support

The following terms define device support levels for Intel® FPGA IP cores:

  • Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
  • Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
  • Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 4.  Device Family Support

Device Family

Support Level

Intel® Stratix® 10 DX

Preliminary support

Intel® Agilex™

Preliminary support

Other device families

No support

Refer to the Intel PCI Express Solutions web page on the Intel website for support information on other device families.

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