P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks

The Write Data Mover has two Avalon® -ST sink interfaces to receive the descriptors that define the data transfers to be executed. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.

The descriptor format for the Write Data Mover is described in the section Descriptor Formats for Data Movers.

Note: The user application is responsible for performing the scheduling between priority and normal queues. No arbitration is performed inside the Write Data Mover.
Table 34.  Write Data Mover Avalon® -ST Normal Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
wrdm_desc_ready_o O When asserted, this ready signal indicates the normal descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. wrdm_desc
wrdm_desc_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_desc_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source 4

[146] : immediate 5

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination PCIe address

[63:0]: source Avalon® -MM address / immediate data

Table 35.  Write Data Mover Avalon® -ST Priority Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
wrdm_prio_ready_o O When asserted, this ready signal indicates the priority descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. wrdm_prio
wrdm_prio_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the priority descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_prio_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source

[146] : immediate

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination PCIe address

[63:0]: source Avalon® -MM address / immediate data

The Write Data Mover internally supports two queues of descriptors. The priority queue has absolute priority over the normal queue, so it should be used carefully to avoid starving the normal queue.

If the Write Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue after it has completed processing the current descriptor. The Write Data Mover resumes processing descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon® -ST source interface.

The Write Data Mover handles one descriptor at a time. When a descriptor has been processed, the Write Data Mover will read the next descriptor from the priority or normal descriptor interface.

Note: There is no buffer to store descriptors inside the Write Data Mover. In Intel's DMA design example, the buffer is located in the external DMA controller and supports up to 128 descriptors.

Software should only send new descriptors when the Write Data Mover has processed all previously sent descriptors. The Write Data Mover indicates the completion of the its data processing by performing an immediate write to the system memory using the last descriptor in the descriptor table. For more details, refer to the Write DMA Example section in the P-tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide (see the link in the Related Information below).

4 When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer. Note that in single source mode, the PCIe address and Avalon® -MM address must be 64-byte aligned.
5 When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported. For immediate transfers, bits [31:0] or [63:0] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary.

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