P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
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2.2.4.3. Root Port Mode

In this mode, the IP core needs to be able to process memory read and write TLPs coming from the DMA controller that resides on the Endpoint side. The following modules are enabled:
  • Bursting Master (in bursting and non-bursting modes)
  • Bursting Slave (in non-bursting mode)
  • Control Register Access
Figure 12. P-Tile Avalon® -MM IP in Root Port Mode

The IP core must be able to generate and process configuration reads and writes to the Endpoint and to the Hard IP configuration registers. This is done via the Configuration Slave. Since the DMA controller resides on the Endpoint side, its control registers need to be programmed by the FPGA local processor. Using the Bursting Slave (in non-bursting mode), the local processor can program the Endpoint control registers for DMA operations. The Endpoint can also send updates of its DMA status to the local processor via the Bursting Master.

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