P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents

1.1. Overview

Note: Do not use this IP for new designs. The P-tile Avalon® Memory-mapped IP for PCI Express* will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.

The P-Tile Avalon® memory-mapped IP for PCI Express combines the functionality of previous Avalon® memory-mapped (Avalon-MM) and Avalon memory-mapped with direct memory access (DMA) interfaces. The IP core using the Avalon-MM interface removes many of the complexities associated with the PCIe protocol. It handles all of the Transaction Layer Packet (TLP) encoding and decoding, simplifying the design task. It also includes optional Read and Write Data Mover modules facilitating the creation of high-performance DMA designs. Both the Avalon-MM interface and the Read and Write Data Mover modules are implemented in soft logic. This IP Core natively supports Endpoint and Root Port configurations with Gen3/Gen4 data rates and x4/x8/x16 link widths. Gen1/Gen2 data rates and x1/x2 link widths are supported via link down-training.

The P-Tile Avalon® memory-mapped IP for PCIe consists of:
  • Modules, implemented in soft logic, that perform Avalon® memory-mapped functions. Together, these modules form an Avalon® memory-mapped Bridge.
  • A PCIe Hard IP that implements the Transaction, Data Link, and Physical layers stack that is compliant with PCI Express Base Specification 4.0 . This stack allows the user application logic in the Intel FPGA to interface with another device via a PCI Express link.

This IP provides support for an Avalon® memory-mapped interface with DMA and is designed to optimize the performance of large-size data transfers. If you want to achieve maximum performance with small-size transfers, Intel recommends the use of the P-Tile Avalon® streaming IP for PCIe.

Note: The P-Tile Avalon® memory-mapped IP for PCIe does not include an internal descriptor controller for DMA operations. This descriptor controller should be implemented in the user application logic. The design example provided for this IP includes an example of a descriptor controller.

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