P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

6.1.1.2. SignalTapII Logic Analyzer

Using the SignalTapII Logic Analyzer, you can monitor the following top-level signals from the P-Tile Avalon® -MM IP for PCI Express to confirm the failure symptom for any port type (Root port, Endpoint or TLP Bypass) and configuration (Gen4/Gen3).

Table 60.  Top-Level Signals to be Monitored for Debugging
Signals Description Expected Value for Successful Link-up
pin_perst_n

Active-low asynchronous input signal to the PCIe Hard IP.

Implements the PERST# function defined by the PCIe specification.

1'b1
p0_reset_status_n

Active-low output signal from the PCIe Hard IP, synchronous to p<n>_app_clk.

Held low until pin_perst_n is deasserted and the PCIe Hard IP comes out of reset, synchronous to p<n>_app_clk.

When port bifurcation is used, there is one such signal for each Avalon® -MM interface.

1'b1
ninit_done Active-low output signal from the PCIe Hard IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. 1'b0
link_up_o

Active-high output signal from the PCIe Hard IP, synchronous to p<n>_app_clk.

Indicates that the Physical Layer link is up.

1'b1
dl_up_o

Active-high output signal from the PCIe Hard IP, synchronous to p<n>_app_clk.

Indicates that the Data Link Layer is active.

1'b1
ltssm_state_o[5:0]

Indicates the LTSSM state, synchronous to p<n>_app_clk.

6'h11 (L0)

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