P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents

2.1. Top-Level Architecture

The P-tile Avalon® -MM IP for PCI Express* consists of the following major sub-blocks:
  • Four PCIe* cores (one x16 core, one x8 core and two x4 cores)
  • Embedded Multi-die Interconnect Bridge (EMIB)
  • Soft logic blocks in the FPGA fabric to implement the Avalon® -MM Bridge, which translates the PCIe TLPs from the PCIe Hard IP into standard Avalon® memory-mapped reads and writes.
Figure 1. P-tile Avalon® -MM IP for PCI Express* top-level block diagram
Note: Each core in the IP implements its own Data Link Layer and Transaction Layer.

The four cores in the IP can be configured to support the following topologies:

Table 9.  Configuration Modes Supported by the P-tile Avalon-MM IP for PCI Express
Configuration Mode Native Hard IP Mode

Endpoint (EP) / Root Port (RP)

Active Cores
Configuration Mode 0 Gen3x16 or Gen4x16


Configuration Mode 1 Gen3x8/Gen3x8 or Gen4x8/Gen4x8


x16, x8
Configuration Mode 2 Gen3x4/Gen3x4/Gen3x4/Gen3x4 or Gen4x4/Gen4x4/Gen4x4/Gen4x4


x16, x8, x4_0, x4_1

In Configuration Mode 0, only the x16 core is active, and it operates in Gen3 x16 mode or Gen4 x16 mode.

In Configuration Mode 1, the x16 core and x8 core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores.

In Configuration Mode 2, all four cores (x16, x8, x4_0, x4_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores.