P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
ID
683268
Date
7/14/2021
Public
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
4.1. Overview
4.2. Clocks and Resets
4.3. Avalon® -MM Interface
4.4. Serial Data Interface
4.5. Hard IP Status Interface
4.6. Interrupt Interface
4.7. Hot Plug Interface (RP Only)
4.8. Power Management Interface
4.9. Configuration Output Interface
4.10. Hard IP Reconfiguration Interface
4.11. PHY Reconfiguration Interface
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.2.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.2.3. Intel Marker (Offset 08h)
A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.2.6. General Purpose Control and Status Register (Offset 0x30)
A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.2.9. Correctable Internal Error Status Register (Offset 0x3C)
A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
2.1.4. Reset
There is only one PERST# (pin_perst_n) pin on P-Tile. Therefore, toggling pin_perst_n will affect the entire P-Tile. If the P-Tile x16 port is bifurcated into two x8 Endpoints, toggling pin_perst_n will affect both x8 Endpoints.
To reset each port individually, use the in-band mechanism like Hot Reset.
Following are the guidelines for implementing the P-Tile pin_perst_n reset signal:
- pin_perst_n is a "power good" indicator from the associated power domain (to which P-Tile is connected). Also, it shall qualify that both the P-Tile refclk0 and refclk1 are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
- pin_perst_n assertion is required for proper Autonomous P-Tile functionality. In Autonomous mode, P-Tile can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and will send out CRS (Configuration Retry Status) until the FPGA fabric is configured and ready.
The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and Soc) is powered up first. P-Tile refclk0 is fed by the on-board free-running oscillator. P-Tile refclk1 driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.
Figure 6. Single PERST# Connection in Bifurcated 2x8 Mode