P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

6.2.2. Enabling the P-Tile Debug Toolkit

To enable the P-Tile Debug Toolkit in your design, enable the option Enable Debug Toolkit in the PCIe Configuration, Debug and Extension options tab of the Intel FPGA P-Tile Avalon® -MM IP for PCI Express.

When using bifurcated ports, you can enable the Debug Toolkit for each bifurcated port by enabling the option Enable Debug Toolkit on each of the bifurcated ports.

Note: When you enable the P-Tile Debug Toolkit in the IP, the Hard IP reconfiguration interface and the PHY reconfiguration interface will be used by the Debug Toolkit. Hence, you will not be able to drive logic on these interfaces from the FPGA fabric.

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