P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. Troubleshooting/Debugging 7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
2. IP Architecture and Functional Description x
2.1. Top-Level Architecture 2.2. Functional Description
2.1. Top-Level Architecture x
2.1.1. Avalon® -MM Bridge Architecture 2.1.2. Clock Domains 2.1.3. Refclk 2.1.4. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview 2.2.4. Avalon® -MM Bridge
2.2.4. Avalon® -MM Bridge x
2.2.4.1. Endpoint Mode with Data Movers 2.2.4.2. Endpoint Mode 2.2.4.3. Root Port Mode
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters 3.3. Avalon-MM Settings
3.2. Core Parameters x
3.2.1. Base Address Registers 3.2.2. PCI Express and PCI Capabilities Parameters 3.2.3. Device Identification Registers 3.2.4. Configuration, Debug and Extension Options
3.2.2. PCI Express and PCI Capabilities Parameters x
3.2.2.1. Device Capabilities 3.2.2.2. Link Capabilities 3.2.2.3. Legacy Interrupt Pin Register 3.2.2.4. MSI Capabilities 3.2.2.5. MSI-X Capabilities 3.2.2.6. Device Serial Number Capability 3.2.2.7. TLP Processing Hints (TPH)
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Interface Reset Signals
4.3. Avalon® -MM Interface x
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) 4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) x
4.3.1.1. Bursting Avalon® -MM Master and Conduit 4.3.1.2. Bursting Avalon® -MM Slave and Conduit 4.3.1.3. Read Data Mover 4.3.1.4. Write Data Mover 4.3.1.5. Descriptor Format for Data Movers 4.3.1.6. Avalon® -MM DMA Operations
4.3.1.1. Bursting Avalon® -MM Master and Conduit x
4.3.1.1.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
4.3.1.2. Bursting Avalon® -MM Slave and Conduit x
4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode
4.3.1.3. Read Data Mover x
4.3.1.3.1. Read Data Mover Avalon® -MM Write Master and Conduit 4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks 4.3.1.3.3. Read Data Mover Status Avalon® -ST Source
4.3.1.4. Write Data Mover x
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit 4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks 4.3.1.4.3. Write Data Mover Status Avalon® -ST Source
4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface) x
4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface 4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface 4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.10. Hard IP Reconfiguration Interface x
4.10.1. Address Map for the User Avalon-MM Interface 4.10.2. Configuration Registers Access
4.10.2. Configuration Registers Access x
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.10.2.2. Using the Debug Register Interface Access
5. Advanced Features x
5.1. PCIe* Port Bifurcation and PHY Channel Mapping
6. Troubleshooting/Debugging x
6.1. Hardware 6.2. Debug Toolkit
6.1. Hardware x
6.1.1. Debugging Link Training Issues 6.1.2. Debugging Data Transfer and Performance Issues
6.1.1. Debugging Link Training Issues x
6.1.1.1. Generic Tools and Utilities 6.1.1.2. SignalTapII Logic Analyzer 6.1.1.3. Additional Debug Tools
6.1.2. Debugging Data Transfer and Performance Issues x
6.1.2.1. Advanced Error Reporting (AER) 6.1.2.2. Second-Level Debug Tools
6.2. Debug Toolkit x
6.2.1. Overview 6.2.2. Enabling the P-Tile Debug Toolkit 6.2.3. Launching the P-Tile Debug Toolkit 6.2.4. Using the P-Tile Debug Toolkit 6.2.5. Enabling the P-Tile Link Inspector 6.2.6. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Intel-Defined VSEC Capability Registers x
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers

4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks

The Write Data Mover has two Avalon® -ST sink interfaces to receive the descriptors that define the data transfers to be executed. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.

The descriptor format for the Write Data Mover is described in the section Descriptor Formats for Data Movers.

Note: The user application is responsible for performing the scheduling between priority and normal queues. No arbitration is performed inside the Write Data Mover.
Table 35.  Write Data Mover Avalon® -ST Normal Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
wrdm_desc_ready_o O When asserted, this ready signal indicates the normal descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. wrdm_desc
wrdm_desc_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_desc_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source 4

[146] : immediate 5

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination PCIe address

[63:0]: source Avalon® -MM address / immediate data

Table 36.  Write Data Mover Avalon® -ST Priority Descriptor Sink Interface
Signal Name Direction Description Platform Designer Interface Name
wrdm_prio_ready_o O When asserted, this ready signal indicates the priority descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3 cycles. wrdm_prio
wrdm_prio_valid_i I When asserted, this signal qualifies valid data on any cycle where data is being transferred to the priority descriptor queue. On each cycle where this signal is active, the queue samples the data.
wrdm_prio_data_i[173:0] I

[173:160]: reserved. Should be tied to 0.

[159:152]: descriptor ID

[151:149] : application specific

[148] : reserved

[147] : single source

[146] : immediate

[145:128]: number of dwords to transfer up to 1 MB

[127:64]: destination PCIe address

[63:0]: source Avalon® -MM address / immediate data

The Write Data Mover internally supports two queues of descriptors. The priority queue has absolute priority over the normal queue, so it should be used carefully to avoid starving the normal queue.

If the Write Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue after it has completed processing the current descriptor. The Write Data Mover resumes processing descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon® -ST source interface.

The Write Data Mover handles one descriptor at a time. When a descriptor has been processed, the Write Data Mover will read the next descriptor from the priority or normal descriptor interface.

Note: There is no buffer to store descriptors inside the Write Data Mover. In Intel's DMA design example, the buffer is located in the external DMA controller and supports up to 128 descriptors.

Software should only send new descriptors when the Write Data Mover has processed all previously sent descriptors. The Write Data Mover indicates the completion of the its data processing by performing an immediate write to the system memory using the last descriptor in the descriptor table. For more details, refer to the Write DMA Example section in the P-tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide (see the link in the Related Information below).

Related Information
4 When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer. Note that in single source mode, the PCIe address and Avalon® -MM address must be 64-byte aligned.
5 When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported. For immediate transfers, bits [31:0] or [63:0] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary.
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