Configuration via Protocol (CvP) is a configuration scheme supported in
Cyclone® 10 GX, and
device families. The CvP configuration scheme creates separate images for the
periphery and core logic. You can store the periphery image in a local configuration device
and the core image in host memory, reducing system costs and increasing the security for the
proprietary core image. CvP configures the
FPGA fabric through the
) link, and is available for Endpoint variants only. This
document describes the CvP configuration scheme for
The CvP configuration scheme has the following advantages:
Reduces system costs by reducing the size of the local flash device that
stores the configuration
Allows update of the FPGA without reprogramming the flash.
Enables dynamic core updates without requiring a system power down. CvP
allows you to update the FPGA core fabric through the
link without a host restart or FPGA full chip reinitialization.
Provides a simpler software model for configuration. A smart host can use
protocol and the application topology to
initialize and update the FPGA core fabric.
Allows quick update of your design for changing application loads.
1.2. CvP System
A CvP system typically consists of an FPGA, a
host, and a configuration device.
Figure 1. CvP Block Diagram
The FPGA connects to the configuration device using the Active Serial x4
(fast mode) configuration scheme.
CvP applications use the
IP block on the
left side of the device only.
You can use other
PCIe Hard IP blocks for PCIe applications. You can select
one of the
Hard IP blocks for CvP, and it must be
on the left side of the device. Once you made this selection, you can't
use the other
Hard IP blocks
Note: To avoid configuration failure,
you must provide a free running and stable reference clock source to
IP core before you start the configuration.
1.3. CvP Modes
The CvP configuration scheme supports the following modes:
CvP Initialization mode
CvP Update mode
CvP Initialization Mode
This mode configures the CvP
using the peripheral image of the FPGA through the on-board configuration device.
Subsequently, configures the core fabric and all GPIOs through
Benefits of using CvP Initialization mode include:
wake-up time requirement
Saving cost by storing the core
image in the host memory
CvP Update Mode
In the CvP update mode, you reconfigure the entire device except the CvP
core after the device enters the user mode
through full chip configuration or CvP initialization. The subsequent core image updates use
link (the periphery must not change during CvP
The CvP update mode uses the same process as root partition reuse in
block-based design, which allows you to reuse the device periphery.
Choose this mode if you want to update the core image for any of the
To change core algorithms logic
To perform standard updates as
part of a release process
To customize core processing
for different components that are part of a complex system
Note: The CvP update mode is
available after the FPGA enters user mode. In user mode, the
link is available for normal
applications as well as to perform an FPGA core image update.
Table 1. CvP Support for
device CvP implementation has the following limitations and restrictions in
the current version of the
Quartus® Prime software:
Only MemWR transactions can be used to write fabric configuration data
to the CvP data register. ConfigWR transactions are not supported.
When you poll the CVP_CREDIT bits from
the CvP credit register, you must write the next 4KB of fabric configuration data to the
CvP data register within 50 ms of receiving an additional credit. Failure to send the data
results in configuration failure.
The CvP response time is variable and depends on different conditions.
The typical delay time is 5 sec and it is safe to wait till 1 min. So the driver should
poll status in credit register to decide on driver timeout.
In CvP initialization and update mode, when FPGA fabric is not
features that uses FPGA fabric
are not accessible.
To generate the update image in the CvP update mode, you must use the
same version of the
Quartus® Prime software that you use to
generate the base image.
22.214.171.124. CvP Error Recovery
This section describes expected behavior during different error
System is unrecoverable and you must power-cycle the
bus error results in
System is unrecoverable and you must power-cycle the
CvP operation requests to stop
Unsupported. Aborting configuration after requesting CvP
operation is not supported.
recommends to power-cycle the system.
A bitstream is provided from a
Quartus® Prime version other than the one used to generate configuration
firmware currently running in the device.
The CVP_CONFIG_ERROR bit in
the CvP status register goes high. Go through the Teardown sequence prior to sending
Flow section for more information on
Note: Mixing bitstreams from different Quartus versions is not
2. CvP Description
2.1. Configuration Images
In CvP, you split your bitstream into two images: periphery image and core
You use the
Quartus® Prime Pro Edition software to
generate the images:
Periphery image (*.periph.jic) — contains all of the periphery. The entire
periphery image is static and cannot be reconfigured.
Core image (*.core.rbf) — contains
all of the core components of the design.
In this mode, an external configuration device stores the periphery
image and it loads into the FPGA through the Active Serial x4 (Fast mode)
configuration scheme. The host memory stores the core image and it loads into the
FPGA through the
After the periphery image configuration is complete, the CONF_DONE signal goes high and the FPGA starts
link training. When
link training is complete, the
link transitions to L0 state and
then allows the host to complete
enumeration of the link. The
initiates the core image configuration through the
to be running prior to sending the periphery image.
After the core image configuration is complete, the CVP_CONFDONE
pin (if enabled) goes high, indicating the FPGA is fully configured.
After the FPGA is fully configured, the FPGA enters user mode. If the
INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is
complete and the FPGA enters the user mode.
In user mode, the
available for normal
2.2.2. CvP Update Mode
CvP update mode is a reconfiguration scheme that allows a host device
to deliver an updated bitstream to a target FPGA device after the device enters user
mode. In this mode, the FPGA device initializes by loading the full configuration
image from the external local configuration device to the FPGA or after CvP
You can perform CvP update on a device that you originally configure
using CvP initialization or any other configuration scheme. CvP initialization is
not a prerequisite for performing CvP update.
In user mode, the
available for normal
applications. You can
use the CvP
link to perform an FPGA core
image update. To perform the FPGA core image update, you can create one or more FPGA
core images in the
Quartus® Prime Pro Edition software that
have identical connections to the periphery image.
Figure 2. Periphery and Core Image Storage Arrangement for CvP Core
Image UpdateThe periphery image remains the same for different core image
updates. If you change the periphery image, you must reprogram the local
configuration device with the new periphery image.
2.3. Compression Features
Quartus® Prime Pro Edition software compresses
device bitstreams to reduce the storage
requirement and increase bitstream processing speed. The periphery and core images are both
2.4. Pin Description
The following table lists the CvP pin descriptions and connection
Table 3. CvP Pin Descriptions and Connection Guidelines
pin indicates the device has received the complete bitstream
during configuration via protocol (CvP) core image
When used for this purpose,
enable this pin using the Intel Quartus Prime
Connect this output pin to an external logic device that
monitors the CvP operation. The VCCIO_SDM power supply must meet
the input voltage specification of the receiving side.
The INIT_DONE pin indicates the device has enter user
mode upon completion of configuration. To use
INIT_DONE to indicate user
mode entry, you must enable it in the
When the INIT_DONE
function is enabled, this pin drives high when
configuration is completed and the device goes into user
recommends you to use SDM_IO0 or SDM_IO16 to implement the
INIT_DONE function when
available as it has an internal weak pull-down for the correct
function of INIT_DONE during
If SDM_IO0 and SDM_IO16 are
unavailable, the INIT_DONE
function can also be implemented using any unused SDM_IO
pins provided that an external 4.7–kΩ pull-down resistor is
provided for the INIT_DONE
CONF_DONE pin indicates
all configuration data has been received.
By default, Intel recommends using the
SDM_IO16 pin to implement the CONF_DONE function. If SDM_IO16 is
unavailable, the CONF_DONE
function can also be implemented using any unused SDM_IO
pins. Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are
required to connect to an external 4.7-kΩ pull-down resistor
for the CONF_DONE signal.
Connect the CONF_DONE pin
to the external configuration controller when configuring
using the Avalon-ST (AVST) interface.
You have an option to monitor this signal
with an external component if you are using the active
serial (AS) x4 configuration scheme
Platform reset pin
implementation, connect the PCIe
signal from the PCIe edge connector to each P-tile transceiver
bank I_PIN_PERST_N input.
Use a level translator to fan out and
change the 3.3V opendrain
signal from the PCIe connector to the 1.8V
I_PIN_PERST_N input of each P-tile
transceiver that is used on the board.
Provide a 1.8V pull-up resistor to the
I_PIN_PERST_N input as the
nPERST signal from the PCIe connector
is an opendrain signal. You must pull up the 3.3V PCIe
nPERST signal on the adapter card.
For non-PCIe systems, connect the
system's master reset signal to the
I_PIN_PERST_N input pin. If the master
reset is not 1.8V, use a level shifter to meet the 1.8V
I_PIN_PERST_N input requirement. For
open-drain master reset driving the
I_PIN_PRST_N input, provide a 1.8V
pull-up resistor. Ensure all power to the device as well as
the PCIe clock is stable prior to releasing the reset to the
This input pin does not have an internal
pull-up resistor, you need to add an external 5kΩ – 10kΩ
pull-up resistor if the voltage translator does not provide
an active driver. If the tile is unused, tie to
Use the single endpoint topology to configure a single FPGA. In this topology,
link connects one
endpoint in the FPGA device to one
root port in the host.
Figure 3. Single Endpoint Topology
3.2. Multiple Endpoints
Use the multiple endpoints topology to configure multiple FPGAs through a
switch. This topology provides you with the
flexibility to select the device to be configured or update through the
link. You can connect any number of FPGAs to the host in
switch controls the core image
configuration through the
link to the targeted
endpoint in the FPGA. You must ensure that the root
port can respond to the
switch and direct the
configuration transaction to the designated endpoint based on the bus/device/function address
of the endpoint specified by the
Figure 4. Multiple Endpoints Topology
4. Design Considerations
4.1. Designing CvP for an Open System
Follow these guidelines when designing an open CvP system where you do not
have complete control of both ends of the
4.1.1. FPGA Power Supplies Ramp Time Requirement
For an open system, you must ensure that your design adheres to the FPGA power
supplies ramp-up time requirement.
The power-on reset (POR) circuitry keeps the FPGA in the reset state until the
power supply outputs are in the recommended operating range. A POR event occurs from when you
power up the FPGA until the power supplies reach the recommended operating range within the
maximum power supply ramp time, tRAMP. If tRAMP is not met, the device I/O pins and programming registers remain
tri-stated, during which device configuration can fail.
To meet the
link up time for CvP, the
total tRAMP must be less
than 10 ms, from the first power supply ramp-up to
the last power supply ramp-up. You must select ASx4 fast mode for MSEL settings to make sure
the shortest POR delay.
Figure 5. FPGA Power Supplies Ramp-Up Time and POR
4.1.2. PCIe Wake-Up Time Requirement
For an open system, you must ensure that the
link meets the
requirement as defined in the
CARD Electromechanical Specification. The transition from
power-on to the link active (L0) state for the
wake-up timing specification must be within 200 ms. The timing from FPGA power-up until the Hard IP
IP Core in the FPGA is ready for link
training must be within 120 ms.
To meet the 120 ms wake-up time
requirement for the
Hard IP in CvP initialization
mode, you need to use periphery image because the configuration time for periphery image is
significantly less than the full FPGA configuration time. You must use the Active Serial x4
(fast mode) configuration scheme for the periphery image configuration.
To ensure successful configuration, all POR-monitored power supplies must ramp
up monotonically to the operating range within the 10
ms ramp-up time. The PERST# signal indicates when the
FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable2. The embedded hard reset controller
triggers after the internal status signal indicates that the periphery image has been loaded.
This reset does not trigger off of PERST#. For CvP
Initialization mode, the
link supports the FPGA core
image configuration and subsequent
Note: For Gen 3/Gen 4 capable
Endpoints, after loading the core bitstream (core.rbf),
Intel recommends to verify that the link has been
trained to the expected Gen
rate. If the link is not operating at Gen 3/Gen 4, software can trigger the Endpoint to
Timing Sequence in CvP
Table 4. Power-Up Sequence Timing in CvP Initialization Mode
Timing Range (ms)
FPGA POR delay time (AS Fast Mode)
Maximum time from the FPGA power up to the end of
periphery configuration in CvP initialization mode (before transceiver
Minimum calibration time before PERST# is deasserted
Minimum transceiver calibration window
Typical transceiver calibration window
signal active from the host
Maximum time from the FPGA power up to the end of
periphery configuration in CvP initialization mode (include transceiver
signal inactive time from the host before the
link enters training state
device must enter L0 after PERST#
Note: 100 ms timing range is only applicable to
Gen 3 does not
need to meet 100 ms timing requirement.
Maximum ramp-up time requirement for all
POR-monitored power supplies in the FPGA to reach their respective operating
2REFCLK must be stable 80 ms after the power supplies are stable in order to
achieve the 145 ms link training complete time
126.96.36.199. For CvP Update Mode
Before you perform CvP update mode, the device must be in user mode.
Note: For Gen
capable Endpoints, in user mode, Intel recommends to verify that the link has been trains to
the expected Gen
rate. If the link is not operating at Gen
software can trigger the Endpoint to retrain.
4.2. Designing CvP for a Closed System
While designing CvP for a closed system where you control both ends of the
link, estimate the periphery configuration time for
CvP Initialization mode or full FPGA configuration time for CvP update mode. You must ensure
that the estimated configuration time is within the time allowed by the
host. Your driver can poll the USERMODE bit of the CvP Status Register to determine if the FPGA enters the user
5. CvP Driver and Registers
5.1. CvP Driver Support
You can develop your own custom CvP driver for Linux using the sample Linux driver
source code provided by
Note: The Linux driver provided by Intel is not a production driver. You must adapt
this driver to your design's strategy.
The CvP driver flow assumes that the FPGA is powered up and the SDM
control block has already configured the FPGA with the periphery image, which is
indicated by the CVP_EN bit in the CvP status register.
Figure 7. CvP Driver Flow
5.3. VSEC Registers for CvP
The Vendor Specific Extended Capability (VSEC) registers occupy byte
offsets 0xD00 to 0xD4C in the
host uses these registers to
communicate with the FPGA control block. The following table shows the VSEC register
map. Subsequent tables provide the fields and descriptions of each register.
Enables/disables the PLD
interface. This allows Host driver to switch the PLD interface out
before USER MODE deasserts, and to switch the PLD interface back in
only after USER MODE has been asserted. This helps to prevent any
glitches or race conditions during the USER MODE switching.
Disable the application layer interface.
0: Enable the application layer interface.
Only change the value of this signal when there has been no
other TLP’s to or from the HIP for 10 us. There should be no TLP’s
issued to the HIP for 10 us after this value changes. When entering
CVP, this bit should be set before CVP_MODE is set. When exiting
CVP, it should be cleared after CVP_MODE is clears. This ensures
that there is no PLD switching during CVP. This field is RW when
cvp_en=1, and RO when cvp_en=0.
Controls whether the Hard IP for
PCI Express is in CVP_MODE or normal mode.
CVP_MODE is active. Signals to the SDM active and all TLPs
are route to the Configuration Space. This CVP_MODE cannot
be enabled if CVP_EN = 0.
The IP core is in normal mode and TLPs are route to the FPGA
recommends to set the reserved bit to 0 for write operation. For
read operations, the
always generates 0 as the output.
5.3.7. CvP Data Registers
Table 12. CvP Data Register (Byte Offsets: 0xD24 - 0xD28)
Write the configuration data to
this register. The data is transferred to the SDM to configure the
Software must ensure that all bytes in
the memory write dword are enabled.
You can access this
register using configuration writes. Alternatively, when in CvP
mode, this register can also be written by a memory write to any
address defined by a memory space BAR for this device. Using memory
writes are higher throughput than configuration writes.
5.3.8. CvP Programming Control Register
Table 13. CvP Programming Control Register (Byte Offset: 0xD2C)
Sets the CvP output to the FPGA
control block indicating the start of a transfer.
When set to 1, the FPGA control
block begins a transfer via CvP.
5.3.9. CvP Credit Register
The credit registers
slow down the transmission of the CvP data to handle back pressure when there is no
buffer space available within the configuration system. The crediting mechanism handles
the back pressure from the configuration system. The total credits register increments
each time an additional 4k buffer is available.
Least significant 8 bits of the
total number of 4k credits granted.
6. Understanding the Design Steps for CvP Initialization using the P-tile in Intel Agilex Devices
6.1. Implementation of CvP Initialization Mode
CvP Initialization mode splits the bitstream into periphery and core images.
The periphery image is stored in a local flash device on the PCB. The core image is stored
in host memory. You must download the core image to the FPGA using the PCI Express link.
You must specify CvP Initialization mode in the
Quartus® Prime Pro Edition software by selecting the CvP Settings Initialization and Update and you must also instantiate the
Intel P-Tile Avalon-ST for PCI Express.
Figure 8. Example Implementation Flow for CvP Initialization
The CvP Initialization demonstration walkthrough includes the following
6.1.1. Generating the Synthesis HDL files for Intel FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe Express
Follow these steps to generate the synthesis HDL files with CvP enabled:
Quartus® Prime Pro Edition software.
On the Tools menu, click Platform Designer. The Open
System window appears.
For System, click + and specify a
File Name to create a new platform
designer system. Click Create.
On the System Contents tab, delete the
clock_in and reset_in components that appear by default.
In the IP Catalog locate and double-click Intel
P-tile Avalon-ST for PCI Express. The new window appears.
On the IP Settings tab,
specify the parameters and options for your design variation.
Note: In case of Gen 3 and Gen 4 x8 variants, only Port 0 implements CvP.
On the Example Designs tab, select the
Simulation option to generate the
testbench, and select the Synthesis
option to generate the hardware design example.
For Generated file format, only
Verilog is available.
Click the Generate Example Design
button. The Select Example Design
Directory dialog box appears. Click OK. The software generates
Quartus® Prime project files for PCI Express reference design. Click
Close when generation completes. An
example design intel_pcie_ptile_ast_0_example_design is created in your project
Click Finish. Close your current project
and open the generated PCI Express example design (pcie_ed.qpf).
Complete your CvP design by adding any desired top-level design and any other
required modules. Pin assignments already being assigned properly based on the
target development kit that user specified earlier.
Note: Reference design for
CvP initialization and update is not available in the current version of the
Quartus® Prime software.
Before testing the design in hardware, you must install the CvP driver in your DUT
system. You can also install RW Utilities or other system verification tools to monitor
the link status of the Endpoint and to observe traffic on the link. You can download
these utilities for free from many web sites.
Note: You can develop your own custom CvP driver for Linux using the
sample Linux driver source code provided by Intel.
188.8.131.52. Installing Open Source CvP Driver in Linux Systems
Download the open source Linux CvP driver from the CvP Driver.
Navigate to the driver directory.
Unzip the drive by typing the following command:
tar -xjvf <driver>.gz
Run the installation by typing the following command:
sudo make install
Once the installation completed successfully, it generates the altera_cvp file under directory /dev/altera_cvp.
184.108.40.206. Setting up the Correct MSEL Switch State
Select Active Serial x4 (Fast mode) for CvP
Table 15. MSEL Pin Settings for
Serial x4 (Fast mode) Scheme of
5 To support AS fast mode, the VCCIO_SDM of
device must be fully ramped-up within 10ms to the
recommended operating conditions. The delay between the
device exiting POR and the SDM Boot-up is shorter for the
fast mode compared to the normal mode. Therefore, AS fast
mode is the recommended configuration scheme for CvP because
the device can conform to the PCIe 100ms power-up-to-active
220.127.116.11. Programming CvP Images
In Active Serial configuration mode, you must program the periphery image
(.periph.jic) into your AS configuration device
and then download the core image (.core.rbf) using
the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled
After loading the periphery image, the
device is triggered to reconfigure from AS to load it. The link should reach the
expected data rate and link width. You can confirm the PCIe link status using the RW
Utilities. Follow these steps to program and test the CvP functionality:
card into the PCI Express slot of the DUT PC
and power it ON.
Quartus® PrimeTools menu and select Programmer.
Click Auto Detect to
verify that the
Intel® FPGA Download Cable recognizes the
Follow these steps to program the periphery image:
device, and then right
click None under File column and select Change File.
Navigate to .periph.jic file and click Open.
Under Program/Configure column, select the respective
Click Start to
program the periphery image into flash.
After the .periph.jic is
programmed, the FPGA must be powered cycle to allow the new peripheral image to
load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate
the link with the new image, power cycle the DUT PC and the
You can use RW Utilities or another system software driver to
verify the link status. You can also confirm expected link speed and
Follow these steps to program the core image:
Copy the .core.rbf
file to your working directory.
Open a console in Linux. Change the directory to the
same mentioned above where the file is copied.
Program the core image by typing the following command: