PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces IP). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.

Note: For Intel® Quartus® Prime software version 18.1 or later, you may see error warning message for design with encrypted IOPLL IP. The auto-generated .sdc files of the IOPLL IP are not supported if you use encryption. You must manually create the .sdc file using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.

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