PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Document Table of Contents

2.6. Design Example

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

Note: The .qsys files are for internal use during design example generation only. You should not edit the files.

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