2.6. Design Example
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.
You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.