PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022

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Document Table of Contents Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent. If PHY Lite for Parallel Interfaces IPs and the External Memory Interface IPs share the same I/O column, you must track the addresses of the interface lanes and the pins.

There are two sets of control registers that store the reconfiguration feature settings:
  • Control/Status registers (CSR) - you can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
  • Avalon® Memory-Mapped registers - you can read and write to these registers using Avalon® interface. The time for the the PHY Lite for Parallel Interfaces delays to change after writing a new value to the registers via the Avalon bus is dependent on the user's configuration. For example, it takes approximately 50 VCO clock cycles for the output delay to change value. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.