PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
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2.2.4.3.1. Strobe Enable Window Calibration

The main block, pstamble_reg, has a gating circuitry to generate dqs_clean from strobe_in/strobe_io and dqs_enable_out signals. The pstamble_reg block has an finite state machine (FSM) to control the gate signal. If dqs_enable_out is high and strobe_in/strobe_io is at any positive edge, the gate signal is asserted and dqs_clean is generated. The dqs_enable_out is high if you set the external signal, rdata_en to high.

An internal counter counts the number of strobe_in/strobe_io toggles until the internal counter reaches the maximum number of toggles. The maximum number of toggles depends on the internal counter. In this example, the internal counter counts eight toggles. Ideally, in normal PHY state, after the maximum number of toggles is reached, the gate signal is deasserted.

Figure 13. Input Path of PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Core

Perform the strobe enable window calibration to capture the correct data­in/data_io on strobe_in/strobe_io signal. You can perform the calibration either by sweeping the dqs_enable_out through the interpolator or sweeping the strobe_in/strobe_io or data_in/data_io.

However, during strobe enable window calibration, while finding the end of the window, an undesired state can happen where the gate signal remains asserted incorrectly and the wrong data­in/data_io (noise) is captured on strobe_in/strobe_io signal. In this case, you must bring PHY to normal state by adding dummy pulses on the strobe_in/strobe_io signal with rdata_en deasserted.

In the following figure, in normal PHY state, the dqs_enable_out is high after the rdata_en signal is high. Once dqs_enable_out is high, if a positive edge of strobe_in/strobe_io is observed, the gate signal goes high (marked by blue marker). An internal counter starts to count at first positive edge of strobe_in/strobe_io until the maximum number of toggles (in this case, the maximum number of toggles is eight). The gate signal is deasserted on the last negative edge of the strobe_in/strobe_io (marked by the green marker). Ideally, dqs_clean is the same as strobe_in/strobe_io because all eight toggles are captured by the internal counter.

In the undesirable state, the strobe_io/strobe_in is calibrated to start toggling earlier. While detecting the correct window margins during calibration, an undesired state occurs because the internal counter does not finish counting to eight resulting in the gate signal remains asserted and produces incomplete dqs_clean (marked by red marker).

Figure 14. dqs_clean Timing Diagram

To return the PHY to the normal state, you must force the gate signal to deassert by adding extra dummy pulses (red strobe_in/strobe_io pulses) while rdata_en is deasserted as shown in the following figure. By adding these dummy pulses, a complete dqs_clean is produced (marked by green marker). After the green marker, although there are few strobe_in/strobe_io toggles, no new dqs_clean is produced because the gate signal remains low.

Figure 15. Adding Extra Dummy Pulses to Return PHY to Normal State

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