PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.3.1. Parameter Settings

Table 12.   PHY Lite for Parallel Interfaces IP Parameter Settings
GUI Name Values Default Values Description
Parameter
Number of groups 1 to 4 1 Number of data and strobe groups in the interface. The value is set to 1 by default.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency

100 MHz - 1200 MHz

533.0 MHz External interface clock frequency.
Use recommended PLL reference clock frequency On, Off On

If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option.

If you want to specify your own PLL reference clock frequency, turn off this option.

PLL reference clock frequency Dependent on interface clock frequency 133.25 MHz PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface.

Select the desired PLL reference clock frequency from the drop-down list. The values in the list changes when you change the interface clock frequency or the user clock rate logic.

VCO clock frequency Calculated internally by PLL 1066.0 MHz The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Clock rate of user logic Quarter, Half, Full Quarter Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz.
Dynamic Reconfiguration
Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces IP settings.
Note: The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP does not support dynamic reconfiguration feature in the Intel® Quartus® Prime v20.3.
I/O Settings
I/O standard

SSTL-12

1.2-V POD

SSTL-12

Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance.

Reference clock I/O configuration

Single-ended,

True Differential with on-chip termination,

True Differential without on-chip termination

Single-ended

Specify the reference clock I/O configuration.

Group <x> - these parameters are set on a per group basis
Group <x> Pin Settings
Pin type Input, Output, Bidirectional Bidirectional Direction of data pins. This value is set to Bidirectional by default.
Pin width 1 to 45 5 9 Number of pins in this data/strobe group. The pin width includes the number of strobe pins.
DDR/SDR DDR, SDR DDR Double/single data rate.
Group <x> Input Path Settings
Read latency 7 to 63 external interface clock cycles 7 Expected read latency of the external device in memory clock cycles.

Refer to the Read Latency table for minimum read latency settings based on FPGA core clock rate.

Capture strobe phase shift 90 90 Internally phase shift the input strobe relative to input data.
Group <x> Output Path Settings
Write latency 0 to 3 0 Additional delay added to the output data in memory clock cycles.

Refer to the Write Latency table for write latency settings based on FPGA core clock rate.

Output strobe phase 0, 45, 90, 135, 180 90 Phase shift of the output strobe relative to the output data.
Group <x> General Strobe Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration Differential, Single-ended Differential

Select the type of strobe.

Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The output path functionality is the same.

Refer to the I/O Standards table for a list of supported I/O standards.

Group <x> OCT Settings
OCT enable size

0 - 15

1 Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data.
Use Default OCT Values On, Off On

Use default OCT values based on the I/O standard parameter setting.

Input OCT Value 60 ohm with calibration, 50 ohm with calibration 6 60 ohm with calibration

Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards table.

Disable the Use Default OCT Values parameter to select the desired input OCT value.

Output OCT Value 34 ohm with calibration, 40 ohm with calibration6 40 ohm with calibration

Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards table supported termination values.

Disable the Use Default OCT Values parameter to select the desired output OCT value.

Pin Placement
Physical Sub-bank ID 0–15 0

ID of the physical sub-bank to be used for placement.

Refer to diagrams in the Intel® Agilex™ I/O Sub-bank Interconnects topic.

Pin Parameter Settings On, Off Off

By default, all the data pins are placed adjacent to each other with no gap between the pins.

Enable this option if require a gap between the data pins.

Refer to the Guidelines: Group Pin Placement topic for pin placement guidelines for PHY Lite for Parallel Interfaces Intel Agilex FPGA IP.

Pin Placement Settings Comma separated values

Enter the location list of the data pins.

Provide the data pins location list in values. For example, enter value of 0, 1, 8, 9 to place data[0] on pin 0, data[1] on pin 1, data[2] on pin 8, and data[3] on pin 9 of the I/O bank. In this case, pin 2 to pin 7 are not used.

Refer to the Guidelines: Group Pin Placement topic for pin placement guidelines for PHY Lite for Parallel Interfaces Intel Agilex FPGA IP.

5 The maximum value varies depending on the configuration, such as number of groups, Quarter Rate/Half Rate/Full Rate, and single-ended or differential PLL reference clock.
6 You can select input OCT value based on your design, ideally through analog simulation using FPGA IBIS modes and specific board.

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