PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: bhc1410941970700

Ixiasoft

Document Table of Contents

4.5.6.2. Timing Constraints and Files

To successfully constrain the timing for PHY Lite for Parallel Interfaces IP, the IP generates a set of timing files. You can locate these timing files in the <variation_name> directory:

  • <variation_name> .sdc
  • <variation_name> _ip_parameters.tcl
  • <variation_name> _pin_map.tcl
  • <variation_name> _parameters.tcl
  • <variation_name> _report_timing.tcl
  • <variation_name> _report_timing_core.tcl