PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.3.2.1. Clock and Reset Interface Signals

Table 15.  Clock and Reset Interface Signals
Signal Name Direction Width Description
ref_clk Input 1 Reference clock for the PLL. The reference clock must be synchronous with group_strobe_in to ensure the dqs_enable signal is in-sync with group_strobe_in.
reset_n Input 1 Resets the interface. Deassertion of this signal should be synchronous to the ref_clk.
interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP to the core logic. This signal indicates that the PLL and PHY circuitry are locked.

Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logic data and control signals.

The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter.

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