126.96.36.199. Clock and Reset Interface Signals
|ref_clk||Input||1||Reference clock for the PLL. The reference clock must be synchronous with group_strobe_in to ensure the dqs_enable signal is in-sync with group_strobe_in.|
|reset_n||Input||1||Resets the interface. Deassertion of this signal should be synchronous to the ref_clk.|
|interface_locked||Output||1||Interface locked signal from PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP to the core logic. This signal indicates that the PLL and PHY circuitry are locked.
Data transfer should starts after the assertion of this signal.
|core_clk_out||Output||1|| Use this core clock in the core-to-periphery transfer of soft logic data and control signals.
The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter.
Did you find the information on this page useful?