PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022

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Document Table of Contents Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation with the corresponding tool.

The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation iterates over each group in your configured IP and performs basic reads/writes to an associated agent (one per group) in the testbench. A simple one group PHY Lite for Parallel Interfaces IP instantiation in the testbench is used for basic address and command outputs to the agent. A side bus between the sim_ctrl and the agents is used to check that the reads and writes are valid.

Figure 52. High-Level View of the Simulation Design Example with One Group