PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.2. Functional Description

The PHY Lite for Parallel Interfaces IP utilizes the I/O subsystem in the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, each column consists of I/O banks and I/O aux. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank.

Figure 56.  Intel® Arria® 10 I/O Bank Structure


Figure 57.  Intel® Cyclone® 10 GX I/O Bank Structure


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