Visible to Intel only — GUID: rsa1601257547629
Ixiasoft
Visible to Intel only — GUID: rsa1601257547629
Ixiasoft
2.2.2. Intel® Agilex™ Input DQS/Strobe Tree
The input DQS/strobe tree is a balanced clock network that distributes the read capture strobe (such as DQS/DQS#) from the external device to the read capture registers inside the I/Os.
The DQS/strobe tree is used for input and bidirectional pin types.
Within every bank, only certain physical pins at specific locations can drive the input DQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary, depending on the size of the group.
Sub-bank Lane used by Data Pins | Group Size | Strobe Pins 1 2 |
---|---|---|
0 | x8 / x9 | Pin 4, 5 |
1 | x8 / x9 | Pin 16, 17 |
2 | x8 / x9 | Pin 28, 29 |
3 | x8 / x9 | Pin 40, 41 |
0, 1 | x18 | Pin 4, 5 |
2, 3 | x18 | Pin 28, 29 |
1, 2 | x36 | Pin 16, 17 |
0, 1, 2 | x36 | Pin 16, 17 |
1, 2, 3 | x36 | Pin 16, 17 |
0, 1, 2, 3 | x36 | Pin 16, 17 |
To target the lower/upper half of GPIO, you must use the Physical Sub-Bank ID as exemplified in the diagrams in the Intel® Agilex™ I/O Sub-bank Interconnects section. For example, if the placement for x18 of sub-bank 0, 1 targets at the top sub-bank of bank 2D in Intel® Agilex™ AGF012 and AGF014 devices, package R24B, enter Physical Sub-Bank ID = 6 at the Pin Placement tab in the PHY Lite IP parameter editor in the Intel® Quartus® Prime Pro Edition software.
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP does not permit QSF-based pin assignment. Instead, the pin placement automatically occurs based on the information from Data/Strobe Pin Placement Within Sub-Bank at the Pin Placement tab in the PHY Lite IP parameter editor in the Intel Quartus Prime software.
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