PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.3.1.2. Write Latency

Table 14.  Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Write Latency (External Memory Clock Cycle)
Quarter rate 1 3
2 3
4 3
8 2

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