PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 18.  I/O Standards and Termination Values for Intel® Agilex™ Devices
I/O Standard Valid Input Terminations (Ω) Valid Output Terminations (Ω) RZQ (Ω)
SSTL-12 50, 60 34, 40 240
1.2-V POD 50, 60 34, 40 240

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