PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
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2.6.1. Generate the Design Example

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

The software generates a user defined directory in which the design example files reside.

There are two variants of design example available for PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP:

  • Design example for variant without dynamic reconfiguration
  • Design example for variant with dynamic reconfiguration
Table 21.   PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Design Example Variants
Design Example Variant Design File Description
Dynamic Reconfiguration On ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel Interfaces IP instance with Calibration IP.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces IP instance with Calibration IP, IOSSM Tester, Tester Core, and Tester I/O.
Off ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel Interfaces IP instance.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces IP instance with Tester Core and Tester I/O.

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